View M5-128120-5YI_385252.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
x High logic densities and I/Os for increased logic integration
x
x
x
x
x x
x
-- 128 to 512 macrocell densities -- 68 to 256 I/Os Wide selection of density and I/O combinations to support most application needs -- 6 macrocell density options -- 7 I/O options -- Up to 4 I/O options per macrocell density -- Up to 5 density & I/O options for each package Performance features to fit system needs -- 5.5 ns tPD Commercial, 7.5 ns tPD Industrial -- 182 MHz fCNT -- Four programmable power/speed settings per block Flexible architecture facilitates logic design -- Multiple levels of switch matrices allow for performance-based routing -- 100% routability and pin-out retention -- Synchronous and asynchronous clocking, including dual-edge clocking -- Asynchronous product- or sum-term set or reset -- 16 to 64 output enables -- Functions of up to 32 product terms Advanced capabilities for easy system integration -- 3.3-V & 5-V JEDEC-compliant operations -- IEEE 1149.1 compliant for boundary scan testing -- 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Por -- PCI compliant (-5/-6/-7/-10/-12 speed grades) -- Safe for mixed supply voltage system design -- Bus-FriendlyTM Inputs & I/Os -- Individual output slew rate control -- Hot socketing -- Programmable security bit Advanced E2CMOS process provides high performance, cost effective solutions Supported by ispDesignEXPERTTM software for rapid logic development -- Supports HDL design methodologies with results optimized for MACH 5 devices -- Flexibility to adapt to user requirements -- Software partnerships that ensure customer success Lattice and Third-party hardware programming support -- LatticePROTM software for in-system programmability support on PCs and Automat Equipment -- Programming support on all major programmers including Data I/O, BP Microsystem and System General
Publication# 20446 Amendment/0
Rev: I Issue Date: September 2000
Table 1. MACH 5 Device Features 1
Feature Supply Voltage (V) Macrocells Maximum User I/O Pins tPD (ns) tSS (ns) tCOS (ns) fCNT (MHz) Typical Static Power (mA) IEEE 1149.1 Boundary Scan Compliant PCI-Compliant M5-128/1 M5LV-128 5 128 120 5.5 3.0 4.5 182 35 Yes Yes 3.3 128 120 5.5 3.0 4.5 182 35 Yes Yes M5-192/1 5 192 120 5.5 3.0 4.5 182 45 Yes Yes M5-256/1 M5LV-256 5 256 160 5.5 3.0 4.5 182 55 Yes Yes 3.3 256 160 5.5 3.0 4.5 182 55 Yes Yes M5-320 M5LV-320 5 320 192 6.52 3.02 5.02 1672 70 Yes Yes 3.3 320 192 6.52 3.02 5.02 1672 70 Yes Yes M5-384 M5LV-384 5 384 160 6.52 3.02 5.02 1672 75 Yes Yes 3.3 384 192 6.52 3.02 5.02 1672 75 Yes Yes
5
2
6
3
5
1
1
Note: 1. "M5-xxx" is for 5-V devices. "M5LV-xxx" is for 3.3-V devices. 2. Preliminary specifications for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.
GENERAL DESCRIPTION
The MACH(R) 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fa at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). Th 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS pro technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Tab 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.
2
MACH 5 Family
Table 2. MACH 5 Speed Grades
Speed Grade1 Device M5-1282 M5-128/1 M5LV-128 M5-192/1 M5-2562 M5-256/1 M5LV-256 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 C C C C C
3
-5 C C C
-6
-7 C C, I C,I C, I C C, I C, I C, I C, I C, I3 C, I3 C, I3 C, I3
-10 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I
-12 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I
-15 C, I C, I I C, I C, I C, I I C, I C, I C, I C, I C, I C, I
C3 C3 C3
Note: 1. C = Commercial grade, I = Industrial grade 2. /1 version recommended for new designs 3. Preliminary specificatons
With Lattice's unique hierarchical architecture, the MACH 5 family provides densities up macrocells to support full system logic integration. Extensive routing resources ensure p retention as well as high utilization. It is ideal for PAL(R) block device integration and a w of other applications including high-speed computing, low-power applications, commu and embedded control. At each macrocell density point, Lattice offers several I/O and p options to meet a wide range of design needs (Table 3).
Table 3. MACH 5 Package and I/O Options 1
M5-128/1 M5LV-128 Supply Voltage 100-pin TQFP 100-pin PQFP 144-pin TQFP 144-pin PQFP 160-pin PQFP 208-pin PQFP 240-pin PQFP 256-ball BGA 352-ball BGA Note: 1. The I/O options indicated with a "*" are obsolete, please contact factory for more information. 104 120 5 68 68 3.3 68, 74 68* 104 104* 120 104* 120 104* 120 160 M5-192/1 5 68 68* M5-256/1 M5LV-256 5 68 68* 3.3 68*, 74 68 104 104* 120 160 120* 160 184* 192 120 160 184* 192* 120* 160 184* 192* 120 160 184* 192* M5-320 M5LV-320 5 3.3 M5-384 M5LV-384 5 3.3
M 5
120*
160
184*
192*
256
MACH 5 Family
Advanced power management options allow designers to incrementally reduce power maintaining the level of performance needed for today's complex designs. I/O safety fe allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-s programmable through an IEEE 1149.1 Test Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. T interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joine block interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the segments together. The only logic difference between any tw 5 devices is the number of segments. Therefore, once a designer is familiar with one de consistent performance can be expected across the entire family. All devices have four c available which can also be used as logic inputs.
Block: 16 MCs CLK 4
Segment Interconnect
Figure 1. MACH 5 Block Diagram
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PA resembles an independent PAL device, it has superior control and logic generation capa
x x x x x
I/O cells Product-term array and Logic Allocator Macrocells Register control generator Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block ca feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block int line to that signal. The interconnect feeder acts as an input switch matrix. The block and interconnects provide connections between any two signals in a device. The block feede block interconnect lines and local feedback lines to the PAL block inputs.
4
MACH 5 Family
Block Interconnect
Segment: 4 Blocks
2 OE Generator Control Generator
32 Logic Alocator Macrocells I/Os Available Clusters C7, C8, C9, C10, C11, C12, C13, C8, C9, C10, C11, C12, C13, C14, C8, C9, C10, C11, C12, C13, C14, C11, C12, C13, C14, C15 Block Feeder Block Interconnect Product-term Array 32 Local Feedback 16
32
Input Register Path
2
Interconnect Feeder
Figure 2. PAL Block Structure
Product-Term Array and Logic Allocator
The product-term array uses the same sum-of-products architecture as PAL devices and c 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluste of-products function with either 3 of 4 product terms.
Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight c three or four product terms, but a given cluster can only be steered to one macrocell (Ta only three product terms in a cluster are steered, the fourth can be used as an input to gate for separate logic generation and/or polarity control.
The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as switch matrix by reassigning logic to macrocells to retain pinout as designs change. The allocation scheme in the MACH 5 device allows for the implementation of large equatio 32 product terms) with only one pass through the logic array.
Table 4. Product Term Steering Options for PT Clusters and Macrocells
Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2, C3, C4 C0, C1, C2, C3, C4, C5 C0, C1, C2, C3, C4, C5, C6 C0, C1, C2, C3, C4, C5, C6, C7 C0, C1, C2, C3, C4, C5, C6, C7 C1, C2, C3, C4, C5, C6, C7, C8 C2, C3, C4, C5, C6, C7, C8, C9 C3, C4, C5, C6, C7, C8, C9, C10 Macrocell M8 M9 M10 M11 M12 M13 M14 M15
C5, C6, C7, C8, C9, C10, C11, C
C6, C7, C8, C9, C10, C11, C12, C
C9, C10, C11, C12, C13, C14, C
C10, C11, C12, C13, C14, C15
MACH 5 Family
Macrocells
The macrocells for MACH 5 devices consist of a storage element which can be configur combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be co as T-type, J-K, or S-R operation through the use of the XOR gate associated with each m
Each PAL block has the capability to provide two input registers by using macrocells 0 a order to use this option, these macrocells must be accessed via the I/O pins associated macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it canno for logic, so its clusters can be re-directed through the logic allocator to another macroc I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the for macrocells 3 and 12 are used to connect to the input registers, these macrocells can used as "buried" macrocells to drive device logic via the matrix.
Control Bus
Macrocell
Logic Allocator 5-8 Clusters/ MC
D
Q
Prog. Polarity
Mode Selection
Figure 3. Macrocell Diagram
Control Generator
The control generator provides four configurable clock lines and three configurable set/rese each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset be independently selected by any flip-flop within a block. The clock lines can be confi provide synchronous global (pin) clocks and asynchronous product term clocks, sum ter and latch enables (Figure 4). Three of the four global clocks, as well as two product-ter and one sum-term clock, are available per PAL block. Positive or negative edge clockin available as well as advanced clocking features such as complementary and biphase cloc Complementary clocking provides two clock lines exactly 180 degrees out of phase, and in applications such as fast data paths. A biphase clock line clocks flip-flops on both the and negative edges of the clock. The configuration options for the four clock lines per P are as follows:
Clock Line 0 Options x x x
Global clock (0, 1, 2, or 3) with positive or negative edge clock enable Product-term clock (A*B*C) Sum-term clock (A+B+C)
6
MACH 5 Family
Clock Line 1 Options x x x
Global clock (0, 1, 2, or 3) with positive edge clock enable Global clock (0, 1, 2, or 3) with negative edge clock enable Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase) Global clock (0, 1, 2, or 3) with clock enable Complement of clock line 2 (same clock enable) Product-term clock (if clock line 2 does not use clock enable
PT (0:3)
Clock Line 2 Options x
Clock Line 3 Options x x
PINCLK (0:3) 0 1 2 3
MUX 4TO1 IN (0) IN (1) IN (2) OUT IN (3) U1 F1 F0 MUX 2TO1 CLKIN Clock Enable PT0 N (0) OUT N (1) F0 /CLK F0 MUX 2TO1 CLK0
PT (0:2) PT0
MUX 4TO1 0 1 2 3 IN (0) IN (1) IN (2) OUT IN (3) U2 F1 F0 /CLK CLK1 CLK PT1 PT2 CLKEN1 BIPHASE CLKEN2 OUT
SET0/RS
MUX 2TO1 PT1 PT1 OUT /PT1(ST) F0
SET1/RS
MUX 2TO1
MUX 4TO1 0 1 2 3 IN (0) IN (1) IN (2) OUT IN (3) U3 F1 F0 PT3 MUX 2TO1 /CLK2 PTCLK F0 CLK3 CLK2 CLKIN Clock Enable MUX 2TO1
PT2
PT2 OUT /PT2 F0
SET2/RST
Block Clocks 0-3
20446G-004
20
Figure 4. Clock Generator
Figure 5. Set/Reset Genera
The set/reset generation portion of the control generator (Figure 5) creates three set/rese the PAL block. Each macrocell can choose one of these three lines or choose no set/res All three lines can be configured for product term set/reset and two of the three lines c configured as sum term set/reset and one of the lines can be configured as product-term term latch enable. While the set/reset signals are generated in the control generator, wh signal sets or resets a flip-flop is determined within the individual macrocell. The same s set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for m configured as latches.
MACH 5 Family
OE Generator
There is one output enable (OE) generator per PAL block that generates two product-ter output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL b choose to be permanently enabled, permanently disabled, or choose one of the two pro output enables per PAL block (Figure 6).
Output Enable Generator
VCC
Internal Feedback External Feedback
Figure 6. Output Enable Generator and I/O Cell
8
MACH 5 Family
MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a device, and at the same time, be easy to understand. This model accurately describes a combinatorial and registered paths through the device, making a distinction between in feedback and external feedback. A signal uses internal feedback when it is fed back into t matrix or block without having to go through the output buffer. The input register spec are also reported as internal feedback. When a signal is fed back into the switch matrix aft gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go through the output buffer to the If a signal goes to the internal feedback rather than to the I/O pad, the parameter desig followed by an "i". By adding tBUF to this internal parameter, the external parameter is For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed for a more detailed discussion about the timing parameters.
(External Feedback)
(Internal Feedback)
COMB/DFF/ LATCH IN tS (S/A) tH (S/A) tSAL tHAL tSRR tCES tCEH tPDi tCO (S/A) i Q tPDLi tGOAi tSRi tBUF
INPUT REG/ INPUT LATCH tSIR (S/A) tHIR (S/A) tSIL tHIL tSRR tCES tCEH tCO (S/A) i Q tPDILi tGOAi tSRi
tBLK tSEG
tPL1 tPL2 tPL3
tPT
CE
SR
tEA tER
CE
SR
PIN CLK
Figure 7. MACH 5 Timing Model
MACH 5 Family
MULTIPLE I/O AND DENSITY OPTIONS
The MACH 5 family offers six macrocell densities in a number of I/O options. This allows to choose a device close to their logic density and I/O requirements, thus minimizing c the same package type, every density has the same pin-out. With proper design conside design can be moved to a higher or lower density part as required.
IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY
Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 This allows functional testing of the circuit board on which the device is mounted throug scan path that can access all critical logic nodes. Internal registers are linked internally, test data to be shifted in and loaded directly onto test nodes, or test node data to be cap shifted out for verification. In addition, these devices can be linked into a board-level s path for more complete board-level testing.
IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rap prototyping, lower inventory levels, higher quality, and the ability to make in-field mod All MACH 5 devices provide in-system programming (ISP) capability through their IEEE compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Bounda Test Access Port as the communication interface through which ISP is achieved, custome benefit of a standard, well-defined interface.
MACH 5 devices can be programmed across the commercial temperature and voltage ra PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. La software takes the JEDEC file output produced by design implementation software, alon information about the Boundary Scan chain, and creates a set of vectors that are used to Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Sc via the parallel port of a PC. Alternatively, LatticePRO software can output files in forma understood by common automated test equipment. This equipment can then be used to MACH 5 devices during the testing of a circuit board.
PCI COMPLIANT
MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V de fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI con clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MA devices provide the speed, drive, density, output enables and I/Os for the most comple designs.
10
MACH 5 Family
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1
Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, wh accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use voltage design capability.
Note: 1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please Application Note titled "Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices".
BUS-FRIENDLY INPUTS AND I/OS
All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry inco two inverters in series which loop back to the input. This double inversion weakly holds at its last driven logic state. While it is a good design practice to tie unused pins to a kno the Bus-Friendly input structure pulls pins away from the input threshold voltage where cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a lo "1." For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and tradeoff can be tailored for each design. The signal speed paths in the lower-power PA will be slower than those in the higher-power PAL blocks. This feature allows speed crit to run at maximum frequency while the rest of the signal paths operate in a lower-pow In large designs, there may be several different speed requirements for different portion design.
Table 5. Power Levels
High Speed/High Power Medium High Speed/Medium High Power Medium Low Speed/Medium Low Power Low Speed/Low Power 100% Power 67% Power 40% Power 20% Power
PROGRAMMABLE SLEW RATE
Each MACH 5 device I/O has an individually programmable output slew rate control bi output can be individually configured for the higher speed transition (3 V/ns) or for the noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow will introduce fewer reflections, less noise, and keep ground bounce to a minimum. Fo with short traces or well terminated lines, the fast slew rate can be used to achieve the speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macro configured to SET on a signal from the control generator, then that macrocell will be SE device power-up. If a macrocell is configured to RESET on a signal from the control gen is not configured for set/reset, then that macrocell will RESET on power-up. To guarant
MACH 5 Family
initialization values, the VCC rise must be monotonic and the clock must be inactive until delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 5 devices as a deterrent to unau copying of the array configuration patterns. Once programmed, this bit defeats readbac programmed pattern by a device programmer, securing proprietary designs from compe Programming and verification are also defeated by the security bit. The bit can only be erasing the entire device.
12
MACH 5 Family
MACH 5 PAL BLOCK
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 Output Enable Output Enable
M0
Macro cell
I/O Cell
M1
Macro cell
I/O Cell
M2
Macro cell
I/O Cell
M3
0
Macro cell
I/O Cell
C0 C1 C2 C3
M4
Macro cell
I/O Cell
M5
Macro cell
I/O Cell
C5
Switch Matrix
C6 C7 C8 C9 C10 C11 C12 C13 C14
63
Logic Allocator
C4
M6
Macro cell
I/O Cell
M7
Macro cell
I/O Cell
M8
Macro cell
I/O Cell
M9
Macro cell
I/O Cell
M10
Macro cell
I/O Cell
C15
M11
Macro cell
I/O Cell
M12
Macro cell
I/O Cell
M13
Macro cell
I/O Cell
M14
Macro cell
I/O Cell
M15
Macro cell
I/O Cell
7
16
Control Generator
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
63 4
32
2
CLK
MACH 5 Family
BLOCK DIAGRAM -- M5(LV)-128/XXX
SEGMENT 0
Block A/Macrocells 0-15 Block D/Macrocells 0-15
16 16 I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 2 16
16 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 PT
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32 I0, 1 2 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 16 7 PT Control 7 Generator 2 PT OE 2 32 Block Interconnect
32
32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 16 Block C/Macrocells 0-15 7 PT Control 7 Generator 2 PT OE
Block B/Macrocells 0-15
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT I NT E R C O N N E CT
Block A/Macrocells 0-15 Block D/Macrocells 0-15
16 16 I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 2 16
16 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 PT
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32 I2, 3 2 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 16 7 PT Control 7 Generator 2 PT OE 2 32 Block Interconnect
32
32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 16 7 PT Control 7 Generator 2 PT OE
Block B/Macrocells 0-15
Block C/Macrocells 0-15
SEGMENT 1
14
MACH 5 Family
SEGMENT 0
Block A/Macrocells 0-15 Block D/Macrocells 0-15
SEGMENT 2
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 Macrocells 2 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 I/O Cells
16 16
16
I/O Cells
16
2 PT OE
2 PT OE Control Generator 7 PT
2
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32 32 I2, I3 2 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 Macrocells 2 I/O Cells 16 16 16 16 64 PT Control 7 Generator 2 PT OE I/O Cells 7 PT Control 7 Generator 2 PT OE 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 2 16
32 Block Interconnect
32
I0
Block Interconnect
32
32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 Block C/Macrocells 0-15 7 PT Control 7 Generator 2 PT OE
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
Macrocells
2
16
Control 7 Generator
2 PT OE
I/O Cells
16
16
BLOCK DIAGRAM -- M5-192/XXX
16
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block B/Macrocells 0-15
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT I NT E R C O N N E CT
Block A/Macrocells 0-15 Block D/Macrocells 0-15
MACH 5 Family
16 16 I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 16 Macrocells 16 16 I/O Cells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 32 I1 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 7 PT Control 7 Generator 2 PT OE 2 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 7 PT Control 7 Generator 32
2 PT OE
2 PT OE
16
SEGMENT 3
Block A/Macrocells 0-15 Block D/Macrocells 0-15 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE Control Generator 7 PT 32 16 16 32 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 Macrocells 2 I/O Cells 16 16 16 Block C/Macrocells 0-15 16 64 PT Control 7 Generator 2 PT OE I/O Cells 16 7 PT Control 7 Generator 2 PT OE 7 PT 32 Macrocells 2 16 64 PT Control 7 Generator 2 PT OE 32 I3 Block B/Macrocells 0-15
SEGMENT 0
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16
16
16
I/O Cells
16
I/O Cells
2 PT OE
2
16 Macrocells
Control Generator
2
16 Macrocells
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32
32
I0
Block Interconnect
32
32
64 x 73 AND Logic Array and Logic Allocator
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
64 PT
Macrocells
2
16
Control 7 Generator
Macrocells
2 PT OE
2
16
I/O Cells
I/O Cells
16
16
16
16
BLOCK DIAGRAM -- M5(LV)-256/XXX
Block B/Macrocells 0-15
Block C/Macrocells 0-15
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT I NT E R C O N N E CT
MACH 5 Family
Block D/Macrocells 0-15 16 16 16 I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 2 PT OE Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 Block Interconnect 32 32 64 x 73 AND Logic Array and Logic Allocator 7 PT Control 7 Generator 2 PT OE 16 2 32 64 PT Macrocells 16 I/O Cells 7 PT Control 7 Generator 2 PT OE 32 I2 64 PT 16
Block A/Macrocells 0-15
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16 16 I/O Cells 2 PT OE 2 16 Macrocells 32 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 2 16
16 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT
16
I/O Cells
2
16 Macrocells
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 7 PT Control 7 Generator 2 PT OE 2 32
32
I1
32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 7 PT Control 7 Generator 2 PT OE
64 x 73 AND Logic Array and Logic Allocator
32
Macrocells
2
I/O Cells
16
SEGMENT 0
Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15
SEGMENT 4
Block A/Macrocells 0-15
16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 32 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 32 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 16 16 I/O Cells
16
16
I/O Cells
2 PT OE
2 32
16 Macrocells
Control Generator
7
32
64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32 32 32 32 Block Interconnect 32 32 64 x 73 AND Logic Array and Logic Allocator 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 Macrocells 2 I/O Cells 16 16 16 Block C/Macrocells 0-15 16 64 PT Control 7 Generator 2 PT OE I/O Cells 16 16 Block C/Macrocells 0-15 Block B/Macrocells 0-15 7 PT Control 7 Generator 2 PT OE 7 PT 32 Macrocells 2 16 64 PT Control 7 Generator 2 PT OE I/O Cells 16 32 64 x 73 AND Logic Array and Logic Allocator 32 Macrocells 2 16 64 PT
I0
Block Interconnect
32
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
Macrocells
2
16
Control 7 Generator
2 PT OE
I/O Cells
16
16
BLOCK DIAGRAM -- M5(LV)-320/XXX
Block B/Macrocells 0-15
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT I NT E R C O N N E CT
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15
MACH 5 Family
16 16 I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 16 Macrocells 16 16 I/O Cells 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 32 I2 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 16 16 7 PT Control 7 Generator 2 PT OE 2 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 7 PT Control 7 Generator 2 PT OE 32 I3 Block B/Macrocells 0-15 Block C/Macrocells 0-15
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16
16
16 16 I/O Cells 2 PT OE 2 16 Macrocells 32 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 2 16
16 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT
16
I/O Cells
16
I/O Cells
2 PT OE
2 PT OE
2
16 Macrocells
Control Generator
2
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
32
32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 16 7 PT Control 7 Generator 2 PT OE 2 32
32
I1
Block Interconnect
32
32
32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 16 7 PT Control 7 Generator 2 PT OE
64 x 73 AND Logic Array and Logic Allocator
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
64 PT
7 PT
Macrocells
2
16
Control 7 Generator
Macrocells
2 PT OE
2
16
Control 7 Generator
2 PT OE
I/O Cells
I/O Cells
16
16
16
16
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
18
SEGMENT 5 SEGMENT 4
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15 16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 32 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 32 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 7 PT 32 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 16 32 32 32 32 Block Interconnect 32 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 Macrocells 2 16 I/O Cells 16 16 Block C/Macrocells 0-15 16 16 16 Block B/Macrocells 0-15 Block C/Macrocells 0-15 64 PT Control 7 Generator 2 PT OE I/O Cells 16 16 7 PT Control 7 Generator 2 PT OE 2 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 Macrocells 2 16 64 PT Control 7 Generator 2 PT OE I/O Cells 16 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 7 PT Control 7 Generator 2 PT OE Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 32 Macrocells 2 16 64 PT I3 32 Block B/Macrocells 0-15
SEGMENT 0
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16
16
16
I/O Cells
16
I/O Cells
2 PT OE
2 PT OE
2
16 Macrocells
Control Generator
2
16 Macrocells
Control Generator
7
7
32
64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
32
I0
Block Interconnect
32
32
64 x 73 AND Logic Array and Logic Allocator
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
64 PT
7 PT
Macrocells
2
16
Control 7 Generator
Macrocells
2 PT OE
2
16
Control 7 Generator
2 PT OE
I/O Cells
I/O Cells
16
16
16
16
BLOCK DIAGRAM -- M5(LV)-384/XXX
Block B/Macrocells 0-15
Block C/Macrocells 0-15
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT I NT E R C O N N E CT
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15
MACH 5 Family
16 16 I/O Cells 2 PT OE 2 16 Macrocells 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Control Generator 7 PT 32 2 16 Macrocells 2 PT OE Control Generator 7 PT 32 16 16 16 I/O Cells 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 32 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Control 7 Generator 2 PT OE I/O Cells 16 16 16 16 16 7 PT 32 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 2 16 7 PT Control 7 Generator 2 PT OE 2 32 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 7 PT Control 7 Generator 2 PT OE 32 16 Block B/Macrocells 0-15 Block C/Macrocells 0-15
Block A/Macrocells 0-15
Block D/Macrocells 0-15
16
16 16 I/O Cells 2 PT OE 2 16 Macrocells 32 Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 2 16
16 I/O Cells 2 PT OE 16 Macrocells Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT
16
I/O Cells
16
I/O Cells
2 PT OE
2
16 Macrocells
Control Generator
2
16 Macrocells
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
32
32 I2 32 64 x 73 AND Logic Array and Logic Allocator 32 64 PT Macrocells 2 16 I/O Cells 16 16 16 7 PT Control 7 Generator 2 PT OE 2 32 Block Interconnect
32
I1
Block Interconnect
32
32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 I/O Cells 16 7 PT Control 7 Generator 2 PT OE
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
Macrocells
2
16
Control 7 Generator
Macrocells
2 PT OE
2
I/O Cells
I/O Cells
16
16
16
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
SEGMENT 1
SEGMENT 2
SEGMENT 3
SEGMENT 0
Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15
SEGMENT 7
Block A/Macrocells 0-15
16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 16 16 I/O Cells
16
16
I/O Cells
2 PT OE
2 32
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32 32 32 32 Block Interconnect 32 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 32 Macrocells 2 16 I/O Cells 16 16 16 Block C/Macrocells 0-15 Macrocells 2 2 PT OE I/O Cells 16 16 Block C/Macrocells 0-15 Block B/Macrocells 0-15 16 Control 7 Generator 64 PT 64 PT Control 7 Generator 2 PT OE I/O Cells 16 7 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT Control 7 Generator 2 PT OE 32 64 x 73 AND Logic Array and Logic Allocator 32 Macrocells 2 16 64 PT
I0
Block Interconnect
32
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
Macrocells
2
16
Control 7 Generator
2 PT OE
I/O Cells
16
16
BLOCK DIAGRAM -- M5(LV)-512/XXX
Block B/Macrocells 0-15
Continued
CLK0 CLK1 CLK2 CLK3
4
S E G M E NT
Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15
MACH 5 Family
16 16 I/O Cells 2 PT OE 2 16 Macrocells 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Control Generator 7 PT 32 2 16 Macrocells 2 PT OE 16 16 I/O Cells 7 PT 32 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 64 PT Macrocells 2 2 PT OE 16 7 PT Control 7 Generator 2 PT OE 32 32 32 64 PT Macrocells 2 16
Block A/Macrocells 0-15
16
16 16 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 2 16 Macrocells I/O Cells 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT
16
I/O Cells
2
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32
32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 7 PT Control 7 Generator 2 PT OE 2 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 7 PT Control 7 Generator 2 PT OE
I1
32
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
Macrocells
2
16
Control 7 Generator
20
SEGMENT 5
Block A/Macrocells 0-15 Block D/Macrocells 0-15 Block D/Macrocells 0-15 16 16 16 I/O Cells I/O Cells 2 PT OE 2 16 Macrocells Control Generator 7 PT 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 2 PT OE 2 16 Macrocells Control Generator 7 PT 32 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 16 16 I/O Cells 32 I3 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 32 Macrocells 2 2 PT OE I/O Cells 16 16 Block B/Macrocells 0-15 16 16 16 Block C/Macrocells 0-15 2 16 Control 7 Generator 64 PT Control 7 Generator 2 PT OE I/O Cells 7 PT 64 PT Macrocells 16 I/O Cells 32 64 x 73 AND Logic Array and Logic Allocator 7 PT Control 7 Generator 2 PT OE 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 2 16 32 32 Block D/Macrocells 0-15 Block A/Macrocells 0-15 Block D/Macrocells 0-15 16 16 I/O Cells 2 PT OE 2 16 Macrocells 7 64 PT 64 x 73 AND Logic Array and Logic Allocator Control Generator 7 PT 32 2 16 Macrocells 2 PT OE 16 16 I/O Cells 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 2 16 Macrocells 16 16 I/O Cells 2 PT OE Control Generator 7 64 PT 64 x 73 AND Logic Array and Logic Allocator 7 PT 7 PT 32 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 7 PT 32 64 PT Macrocells 2 16 7 PT Control 7 Generator 2 PT OE 32 I2 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 2 16 7 PT Control 7 Generator 2 PT OE 2 32 32 Block Interconnect 32 64 x 73 AND Logic Array and Logic Allocator 64 PT Macrocells 16 7 PT Control 7 Generator 2 PT OE 32 2 PT OE
SEGMENT 6
Block A/Macrocells 0-15
16
16
I/O Cells
16
2 PT OE
2
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
7 PT
32
32
Block Interconnect
32
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
7 PT
32
Macrocells
2
16
Control 7 Generator
2 PT OE
I/O Cells
16
16
16
BLOCK DIAGRAM -- M5(LV)-512/XXX
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Continued
I NT E R C O N N E CT
MACH 5 Family
Block A/Macrocells 0-15
16
16
I/O Cells
2
16 Macrocells
Control Generator
32
7 64 PT 64 x 73 AND Logic Array and Logic Allocator
32
32
64 x 73 AND Logic Array and Logic Allocator
32
64 PT
Macrocells
2
16
Control 7 Generator
ABSOLUTE MAXIMUM RATINGS
M5
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Device Junction Temperature (Note 1) . . . . . . . . . . . +130C or +150C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (-40C to +85C) . . . . . . . . . . 200 mA
Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0
Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40 Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5
Operating ranges define those limits between wh functionality of the device is guaranteed.
5-V DC CHARACTERISITICS OVER OPERATING RANGES
Parameter Symbol Parameter Description Output HIGH Voltage (For M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384, M5-512 Devices) Output HIGH Voltage (For M5-128, M5-192, M5-256 Devices) VOL VIH VIL IIH IIL IOZH IOZL ISC Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Test Description IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOH = 0 mA, VCC = Max, VIN = VIH or VIL IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOH = -2.5 mA, VCC = 5.25 V, VIN = VIH or VIL IOL = +16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3) Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) VIN = 5.25, VCC = Max (Note 4) VIN = 0, VCC = Max (Note 4) VOUT = 5.25, VCC = Max, VIN = VIH or VIL (Note 4) VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 4) VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 5) -30 2.0 2.4 Min 2.4 Typ
M
VOH
3
3
0
0
1
-
1
-
-1
Note: 1. 150 for M5-128, M5-192 and M5-256 devices. 130 for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5
2. Total IOL between ground pins should not exceed 64 mA. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are in 4. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.
5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second
MACH 5 Family
ABSOLUTE MAXIMUM RATINGS
M5LV
Storage Temperature . . . . . . . . . . . . . .-65C to +150C Device Junction Temperature . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V Latchup Current (-40C to +85C) . . . . . . . . . . 200 mA
Str esses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0 Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0
Industrial (I) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40 Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0
Operating ranges define those limits between wh functionality of the device is guaranteed.
3.3-V DC CHARACTERISITICS OVER OPERATING RANGES
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL Test Description IOH = -100 A IOH = 3.2 mA IOL = 100 A IOL = 16 mA (Note 1) 2.0 -0.3 Min VCC -0.2 2.4
Ma
0.2
0.5
VOUT VOH Min or VOUT VOL Max (Note 2) VOUT VOH Min or VOUT VOL Max (Note 2) VIN = 3.6, VCC = Max (Note 3) VIN = 0, VCC = Max (Note 3) VOUT = 3.6, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 4)
5.5
0.8
10
-10
10 -15
-10
-16
Notes: 1. Total IOL between ground pins should not exceed 64 mA. 3. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.
2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are in
4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one secon
22
MACH 5 Family
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1
-5 Min Combinatorial Delay: tPDi tPD tSS tSA tHS tHA tCOSi tCOS tCOAi tCOA tSAL tHAL tPDLi tPDL tGOAi tGOA Internal combinatorial propagation delay Combinatorial propagation delay Synchronous clock setup time Asynchronous clock setup time Synchronous clock hold time Asynchronous clock hold time Synchronous clock to internal output Synchronous clock to output Asynchronous clock to internal output Asynchronous clock to output Latch setup time Latch hold time Transparent latch internal Propagation delay through transparent latch Gate to internal output Gate to output Input register setup time using a synchronous clock Input register setup time using an asynchronous clock Input register hold time using a synchronous clock Input register hold time using an asynchronous clock Input latch setup time Input latch hold time Transparent input latch Output buffer delay Slow slew rate delay Output enable time Output disable time 3.0 3.0 6.0 8.0 7.0 9.0 3.0 3.0 0.0 3.0 2.5 4.5 6.0 8.0 4.0 3.0 7.0 9.0 8.0 10.0 3.5 5.5 3.0 3.0 0.0 3.0 3.0 5.0 6.0 8.0 4.0 4.0 7.0 9.0 8.0 10.0 4.5 6.5 4.0 4.0 0.0 4.0 4.0 6.0 8.0 10.0 5.0 5.0 8.0 10.0 9.0 11.0 5.5 7.5 5.0 5.0 0.0 5.0 5.0 7.0 10.0 12.0 6.0 6.0 9.0 11.0 10.0 12.0 8.0 10.0 6.0 6.0 0.0 6.0 6.0 8.0 13.0 15.0 7.0 7.0 10.0 12.0 11.0 13.0 10.0 12.0 8.0 7.0 0.0 7.0 8.0 10.0 15.0 17.0 13.0 15.0 Max Min -6 Max Min -7 Max -10 Min Max -12 Min Max -15 Min Max
Min
Registered Delays:
10.0
8.0
0.0
8.0
Latched Delays:
8.0
8.0
Input Register Delays: tSIRS tSIRA tHIRS tHIRA 2.0 0.0 3.0 6.0 2.0 0.0 3.0 6.0 2.0 0.0 3.0 6.0 3.0 0.0 4.0 7.0 3.0 0.0 4.0 7.0 3.0 0.0 4.0 7.0
3.0
0.0
4.0
7.0
Input Latch Delays: tSIL tHIL tPDILi tBUF tSLW tEA tER 2.0 6.0 5.0 2.0 2.5 7.5 7.5 2.0 6.0 5.0 2.0 2.5 7.5 7.5 2.0 6.0 5.5 2.0 2.5 9.5 9.5 3.0 7.0 6.0 2.0 2.5 10.0 10.0 3.0 7.0 6.0 2.0 2.5 12.0 12.0 3.0 7.0 6.0 2.0 2.5 15.0 15.0
3.0
7.0
Output Delays:
MACH 5 Family
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINU
-5 Min Power Delays: tPL1 tPL2 tPL3 Power level 1 delay (Note 2) Power level 2 delay (Note 2) Power level 3 delay (Note 2) 4.0 (5.0) 6.0 (9.0) 9.0
(17.5)
-6 Max Min Max Min
-7 Max 4.0 (5.0) 6.0 (9.0) 9.0
(17.5)
-10 Min Max 4.0 (5.0) 6.0 (9.0) 9.0
(17.5)
-12 Min Max 4.0 (5.0) 6.0 (9.0) 9.0
(17.5)
-15 Min Max 4.0 (5.0) 6.0 (9.0) 9.0
(17.5)
Min
4.0 6.0 9.0
Additional Cluster Delay: tPT tBLK tSEG Product term cluster delay Block interconnect delay Segment interconnect delay Asynchronous reset or preset to internal register output Asynchronous reset or preset to register output Reset and set register recovery time Asynchronous reset or preset width Clock enable setup time Clock enable hold time Global clock width low (Note 3) Global clock width high (Note 3) Product term clock width low Product term clock width high Gate width low (for low transparent) or high (for high transparent) Input register clock width low or high 5.5 3.0 4.0 3.0 2.5 2.5 3.0 3.0 3.0 3.0 0.3 1.5 4.5 0.3 1.5 4.5 0.3 1.5 5.0 0.3 2.0 6.0 0.3 2.0 6.0 0.3 2.0 6.0 Interconnect Delays:
Reset and Preset Delays: tSRi tSR tSRR tSRW tCES tCEH Width: tWLS tWHS tWLA tWHA tGWA tWIR 3.0 3.0 4.0 4.0 4.0 4.0 3.0 3.0 4.0 4.0 4.0 4.0 4.0 4.0 5.0 5.0 5.0 5.0 5.0 5.0 6.0 6.0 6.0 6.0 6.0 6.0 7.0 7.0 7.0 7.0 6.0 8.0 7.5 4.0 5.0 4.0 8.0 10.0 7.5 4.0 5.0 4.0 8.0 10.0 8.0 5.0 6.0 5.0 10.0 12.0 9.0 6.0 7.0 6.0 12.0 14.0 10.0 7.0 7.0 6.0 14.0 16.0
11.0
8.0
Clock Enable Delays:
8.0
7.0
6.0
6.0
8.0
8.0
8.0
8.0
24
MACH 5 Family
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINU
-5 Min Frequency: External feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) fMAX Internal feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS +tCOSi) No feedback PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tHS) External feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA) fMAXA Internal feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA +tCOAi) No feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tHA) fMAXI Maximum input register frequency 1/(tSIRS+tHIRS) or 1/(2 x tWICW) 133 182 200 91 111 167 167 125 167 167 91 111 125 125 100 125 167 71.4 83.3 125 125 83.3 100 125 58.8 66.7 100 100 71.4 83.3 100 47.6 52.6 83.3 83.3 55.6 62.5 83.3 41.7 45.5 71.4 71.4 Max Min -6 Max Min -7 Max -10 Min Max -12 Min Max -15 Min Max
Min
45.5
50.0
83.3
35.7
38.5
62.5
62.5
Notes: 1. See "MACH Switching Test Circuits" documentation on the Lattice Data Book CD-ROM or Lattice web site. 2. Numbers in parentheses are for M5-128, M5-192, M5-256. 3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).
MACH 5 Family
CAPACITANCE1
Parameter Symbol CIN CI/O Parameter Description I/CLK pin I/O pin Test conditions VIN =2.0 V VOUT =2.0 V 3.3 V or 5 V, 25 C, 1 MHz 3.3 V or 5 V, 25 C, 1 MHz Typ 12 10
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is mo these parameters may be affected.
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system fr The selected "typical" pattern is a 16-bit up-down counter. This pattern fills the device a exercises every macrocell. Maximum frequency shown uses internal feedback and a Dregister. Power/Speed are optimized to obtain the highest counter frequency and the lo power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to power. The lowest frequency signals (MSBs) are placed in a common PAL block and se lowest power. For a more detailed discussion about MACH 5 power consumption, refer application note entitled MACH 5 Power in the Application Notes section on the Lattice D CD-ROM or Lattice web site.
ICC CURVES AT HIGH /LOW POWER MODES
VCC = 5 V or 3.3 V, TA = 25 C 700 M5(LV)-512 high
600
M5(LV)-384 hi 500
M5(LV)-320 hi ICC (mA) 400
M5-256/1 M5LV-25
300
M5-192/1 h 200
100
M5-128/1 and M5LV-128 h M5(LV)-512 low power M5(LV)-384 low power M5(LV)-320 low power M5-256/1 and M5LV-256 low power M5-192/1 low power M5-128/1 and M5LV-128 low power
0 100 110 120 130 140 10 20 30 40 50 60 70 80 90 0
Frequency (MHz)
Figure 8. ICC Curves at High/Low Power Modes
26
MACH 5 Family
VCC = 5 V, TA = 25 C 700
M5-256 high pow 600
500
M5-192 high
ICC (mA)
400 M5-128 high power
300
200 M5-256 low power 100 M5-192 low power M5-128 low power
0 100 110 120 130 10 20 30 40 50 60 70 80 90 0
Frequency (MHz)
Figure 9. ICC Curves at High/Low Power Modes
MACH 5 Family
100-PIN PQFP CONNECTION DIAGRAM
Top View
100-Pin PQFP (68 I/O)
0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2
M5-128 M5LV-128* M5-192* M5-256* M5LV-256
M5-128 M5LV-128* M5-192* M5-256* M5LV-256
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0
0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12
GND GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 VCC GND GND VCC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52
3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND GND VCC VCC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS GND GND
3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
2A12 2B13 2B12 2B11 2B8 2B7 2B4 2B3 2B2
0D1 0C1 0C1 0C1 0C8 0C7 0C4 0C3 0C2
2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12
2C2 2C3 2C4 2C7 2C8 2C11 2C12 2C13 2D12
1C2 1C3 1C4 1C7 1C8 1C1 1C1 1C1 1D1
M5-256* M5LV-256 M5-192* M5-128 M5LV-128* *Package obsolete, contact factory.
I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
M5-256* M5LV-256 M5-192*
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
M5-128 M5LV-128*
20446G-016
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
3
D
15
Macrocell ( PAL Block
Segment (0
28
MACH 5 Family
100-PIN TQFP CONNECTION DIAGRAM - 68 I/O
Top View
100-Pin TQFP (68 I/O)
M5-128 M5LV-128 M5-192 M5-256 M5LV-256*
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13
0A13 0A12 0A11 0A8 0A7 0A4 0A3 0A2
M5M5-256 M5LV-256*
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0
0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND GND NC I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 VCC GND GND VCC NC I/O59 I/O58 I/O57 I/O56 I/O55 I/O54 I/O53 I/O52 GND
3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7
GND TDO I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I/O45 I/O44 I/O43 I3/CLK3 GND VCC I2/CLK2 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I/O35 I/O34 TMS
3A12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
2 2 2 2 2 2 2 2 2
2B2 2B3 2B4 2B7 2B8 2B11 2B12 2B13 2A12
2 2 2 2 2 2 2 2 2
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
M5-256 M5LV-256* M5-192 M5-128 M5LV-128 *Package obsolete, contact factory.
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
GND GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 NC VCC GND GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 GND GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
M5-256 M5LV-256*
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
M5-
1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13
3
D
15
Macrocell
PAL Block
Segment (
MACH 5 Family
100-PIN TQFP CONNECTION DIAGRAM - 74 I/O
Top View
100-Pin TQFP (74 I/O)
M5LV-128 M5LV-256 0D1 0D2 0D3 0D4 0D7 0D8 0D11 0D12 0D13 3D12 3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A4 0A3 0A2 0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D11 0D12
M5LV-
0A14 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
0A12 0B13 0B12 0B11 0B8 0B7 0B4 0B3 0B2
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A14
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13 1A12
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I0/CLK0 VCC GND GND I1/CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O55 GND
GND TDO I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I/O47 I/O46 I3/CLK3 GND VCC I2/CLK2 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I/O39 I/O38 I/O37 TMS
3 3 3 3 3 3 3 3 3
2B 2B 2B 2B 2B 2B 2B 2B 2A
M5LV-256 M5LV-128
GND 1A13 1A7 I/O18 1A12 1A6 I/O19 1A11 1A5 I/O20 1A10 1A4 I/O21 1A8 1A3 I/O22 1A7 1A2 I/O23 1A4 1A1 I/O24 1A3 1A0 I/O25 1A2 1D11 I/O26 1A1 1D12 1/O27 VCC GND GND VCC 1D2 2D12 I/O28 1D3 2A0 I/O29 1D4 2A1 I/O30 1D7 2A2 I/O31 1D8 2A3 I/O32 1D10 2A4 I/O33 1D11 2A5 I/O34 1D12 2A6 I/O35 1D13 2A7 1/O36 GND
M5LV-
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
3
D
15
Macrocell
PAL Block
Segment (
30
MACH 5 Family
144-PIN PQFP CONNECTION DIAGRAM
Top View
144-Pin PQFP
M5-128 M5LV-128* M5-192*
0D8 0D11 0D12 0D13 2A2 2A3
0A11 0A10 0A8 0A7 0A6 0A5 0A4
2A4 2A5 2A6 2A7 2A8 2A10 2A11
0D6 0D7 0D8 0D10 0D11 0D12 0D13
0A13 0A12 0A11 A10 0A8 0A7 0A6
0D0 0D1 0D2 0D3 0D4 0D5
0A5 0A4 0A3 0A2 0A1 0A0
0D3 0D4 0D7 0D8 0D11 0D12
0A3 0A2 0D2 0D3 0D4 0D7
M
0A7 0A6 0A5 0A4 0A3 0A2 0A1
0A14 0B13 0B12 0B11 0B10 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1
0A12 0A13 0A14 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 0B1 0B0
0A8 0A9 0A10 0A11 0A12 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B10 1B11 1B12 1B13 1A14
1B0 1B1 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A14 1A13 1A12
1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A12 1A11 1A10 1A9 1A8
TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 VCC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND VCC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 VCC GND GND VCC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 VCC GND
3A1 3A2 3A3 3A4 3A5 3A6 3A7
M5-256* M5LV-256*
3D12 3D11 3D8 3D7 3D4 3D3
M5-256* M5LV-256*
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND VCC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS
3A8 3A9 3A10 3A11 3A12
3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2
2B2 2B3 2B4 2B5
2B8 2B11 2B12 2B13
2A12 2A11 2A10 2A9 2A8
1A7 1A6 1A5 1A4 1A3 1A2 1A1
1D3 1D4 1D7 1D8 1D11 1D12
2D12 2D11 2D8 2D7 2D4 2D3
M5-256* M5LV-256* M5-192* M5-128 M5LV-128*
2A1 2A2 2A3 2A4 2A5 2A6 2A7
GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 VCC GND GND VCC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
M5-256* M5LV-256*
1A11 1A10 1A8 1A7 1A6 1A5 1A4
1A3 1A2 1D2 1D3 1D4 1D7
1D8 1D11 1D12 1D13 2D2 2D3
2D4 2D5 2D6 2D7 2D8 2D10 2D11
M
1A13 1A12 1A11 1A10 1A8 1A7 1A6
1A5 1A4 1A3 1A2 1A1 1A0
1D0 1D1 1D2 1D3 1D4 1D5
*Package obsolete, contact factory.
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
1D6 1D7 1D8 1D10 1D11 1D12 1D13
3
D
15
Macrocell
PAL Block
Segment (
MACH 5 Family
144-PIN TQFP CONNECTION DIAGRAM
Top View
144-Pin TQFP
0D0 0D1 0D2 0D3 0D4 0D5 3D12 3D11 3D8 3D7 3D4 3D3 0A5 0A4 0A3 0A2 0A1 0A0 M5LV-128 0D6 0D7 0D8 0D10 0D11 0D12 0D13 0A13 0A12 0A11 A10 0A8 0A7 0A6
0A7 0A6 0A5 0A4 0A3 0A2 0A1
0A14 0B13 0B12 0B11 0B10 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1
0A8 0A9 0A10 0A11 0A12 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B10 1B11 1B12 1B13 1A14
1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A12 1A11 1A10 1A9 1A8
TDI I/O0 I/O1 I/O2 I/O3 I/O4 GND I/O5 I/O6 I/O7 I/O8 GND I/O9 I/O10 I/O11 I/O12 I0/CLK0 VCC GND I1/CLK1 I/O13 I/O14 I/O15 I/O16 GND I/O17 I/O18 I/O19 I/O20 GND I/O21 I/O22 I/O23 I/O24 I/O25 TCK
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND VCC I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 GND I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 VCC GND GND VCC I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 GND I/O84 I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 VCC GND
3A1 3A2 3A3 3A4 3A5 3A6 3A7
M5LV-256
0D3 0D4 0D7 0D8 0D11 0D12
M5L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TDO I/O77 I/O76 I/O75 I/O74 I/O73 GND I/O72 I/O71 I/O70 I/O69 GND I/O68 I/O67 I/O66 I/O65 I3/CLK3 GND VCC I2/CLK2 I/O64 I/O63 I/O62 I/O61 GND I/O60 I/O59 I/O58 I/O57 GND I/O56 I/O55 I/O54 I/O53 I/O52 TMS
1A7 1A6 1A5 1A4 1A3 1A2 1A1
1D3 1D4 1D7 1D8 1D11 1D12
2D12 2D11 2D8 2D7 2D4 2D3
M5LV-256
2A1 2A2 2A3 2A4 2A5 2A6 2A7
GND VCC I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 GND I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 VCC GND GND VCC I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 GND I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND
M5L
1A13 1A12 1A11 1A10 1A8 1A7 1A6
1A5 1A4 1A3 1A2 1A1 1A0
1D0 1D1 1D2 1D3 1D4 1D5
M5LV-128
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
1D6 1D7 1D8 1D10 1D11 1D12 1D13
3
D
15
Macrocell
PAL Block
Segment (
32
MACH 5 Family
160-PIN PQFP CONNECTION DIAGRAM
Top View
160-Pin PQFP (128, 192, 256 Macrocells)
0D6 0D7 0D8 0D9 0D10 0D11 0D12 0D13 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 0A13 0A12 0A11 0A10 0A9 0A8 0A7 0A6 0D0 0D1 0D2 0D3 0D4 0D5 3D12 3D11 3D8 3D7 3D4 3D3 0D8 0D11 0D12 0D13 2A2 2A3 0A5 0A4 0A3 0A2 0A1 0A0 0D3 0D4 0D7 0D8 0D11 0D12 0A3 0A2 0D2 0D3 0D4 0D7 M5-128 M5LV-128 M5-192
M5-256 M5LV-256
0A11 0A10 0A9 0A8 0A7 0A6 0A5 0A4
M5-256 M5LV-256
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0
0A14 0A15 0B14 0B13 0B12 0B11 0B10 0B9 0B8 0B7 0B6 0B5 0B4 0B3 0B2 0B1
0A12 0A13 0A14 0A15 0B15 0B14 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2 0B1 0B0
0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15 0B13 0B12 0B11 0B8 0B5 0B4 0B3 0B2
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13 1B14 1A15 1A14
1B0 1B1 1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1B14 1B15 1A15 1A14 1A13 1A12
1B2 1B3 1B4 1B5 1B8 1B11 1B12 1B13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND VCC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND VCC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 VCC GND GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 VCC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 VCC GND
3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7
TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND VCC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS
3A8 3A9 3A10 3A11 3A12 3A13 3A14 3A15
3B13 3B12 3B11 3B8 3B5 3B4 3B3 3B2
2B2 2B3 2B4 2B5 2B8 2B11 2B12 2B13
2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
1D3 1D4 1D7 1D8 1D11 1D12
2D12 2D11 2D8 2D7 2D4 2D3
M5-256 M5LV-256 M5-192
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCC GND GND VCC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 VCC GND
M5-256 M5LV-256
1A11 1A10 1A9 1A8 1A7 1A6 1A5 1A4
1A3 1A2 1D2 1D3 1D4 1D7
1D8 1D11 1D12 1D13 2D2 2D3 1D0 1D1 1D2 1D3 1D4 1D5
1A13 1A12 1A11 1A10 1A9 1A8 1A7 1A6
1A5 1A4 1A3 1A2 1A1 1A0
M5-128 M5LV-128
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
1D6 1D7 1D8 1D9 1D10 1D11 1D12 1D13
2D4 2D5 2D6 2D7 2D8 2D9 2D10 2D11
3
D
15
Macrocell
PAL Block
Segment (
MACH 5 Family
160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGR
Top View
160-Pin PQFP (320, 384, 512 Macrocells)
0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 4A12 4A11 4A8 4A7 4A4 4A3 4B3 4B4 4B7 4B8 4B11 4B12 5B3 5B4 5B7 5B8 5B11 5B12 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2
M5-320* M5LV-320 M5-384* M5LV-384 M5-512* M5LV-512
0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13
5A12 5A11 5A8 5A7 5A4 5A3
M M5-512* M5LV-512
7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2
7B3 7B4 7B7 7B8 7B11 7B12
6B12 6B11 6B8 6B7 6B4 6B3
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 0D13 0D12 0D11 0D8 0D7 0D4 0D3 0D2
1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8
1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
1D2 1D3 1D4 1D7 1D8 1D11 1D12 1D13 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND VCC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND VCC I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 VCC GND GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 VCC GND I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 VCC GND
6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13
TDO I/O91 I/O90 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 GND I/O83 I/O82 I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I3/CLK3 GND VCC I2/CLK2 I/O75 I/O74 I/O73 I/O72 I/O71 I/O70 I/O69 I/O68 GND I/O67 I/O66 I/O65 I/O64 I/O63 I/O62 I/O61 I/O60 TMS
5A2 5A3 5A4 5A7 5A8 5A11 5A12 5A13
5D13 5D12 5D11 5D8 5D7 5D4 5D3 5D2
4D2 4D3 4D4 4D7 4D8 4D11 4D12 4D13
4A13 4A12 4A11 4A8 4A7 4A4 4A3 4A2
2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2
2B3 2B4 2B7 2B8 2B11 2B12
3B12 3B11 3B8 3B7 3B4 3B3
M5-512* M5LV-512 M5-384* M5LV-384 M5-320* M5LV-320
3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13
GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCC GND GND VCC I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 VCC GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 VCC GND
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
M5-512* M5LV-512
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13
2A12 2A11 2A8 2A7 2A4 2A3
2B3 2B4 2B7 2B8 2B11 2B12
3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
M
1B3 1B4 1B7 1B8 1B11 1B12
2B12 2B11 2B8 2B7 2B4 2B3
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
*Package obsolete, contact factory.
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
7
D
15
Macrocell
PAL Block
Segment (
34
MACH 5 Family
1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8 1B2 1B3 1B4 1B5 0B5 0B4 0B3 0B2
1B6 1B7 1B8 1B9 1B10 1B11 1B12 1B13
0B13 0B12 0B11 0B10 0B9 0B8 0B7 0B6
0A8 0A9 0A10 0A11 0A12 0A13 0A14 0A15
M5-256 M5LV-256
M5-256 M5LV-256
Top View
Pin Designations
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 VCC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
0A7 0A6 0A5 0A4 0A3 0A2 0A1 0A0 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0D10 0D11 0D12 0D13
208-PIN PQFP CONNECTION DIAGRAM
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
VCC TDI TCK TMS TDO
= = = = =
1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
208-Pin PQFP (192, 256 Macrocells)
MACH 5 Family
1D10 1D11 1D12 1D13
2D13 2D12 2D11 2D10
3D13 3D12 3D11 3D10
3
2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2
3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2
D
15
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 VCC GND GND VCC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND VCC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 VCC GND GND VCC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 VCC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND
3A0 3A1 3A2 3A3 3A4 3A5 3A6 3A7
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Macrocell
Segment (
PAL Block
208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGR
Top View
208-Pin PQFP (320, 384, 512 Macrocells)
0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15 4A7 4A4 4A3 4A2 4B2 4B3 4B4 4B7 M5-320 M5LV-320 M5-384 M5LV-384 M5-512 M5LV-512 3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2 6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13 4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2
0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13
5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8
7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2
7B8 7B11 7B12 7B13
6B13 6B12 6B11 6B8
5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15
5A7 5A4 5A3 5A2
5B2 5B3 5B4 5B7
M5 M5LV
7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13
0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2
0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2
0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 0D7 0D4 0D3 0D2
1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15
1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15
1D2 1D3 1D4 1D7 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15
1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8
1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2
TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I0/CLK0 VCC GND I1/CLK1 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
GND I/O159 I/O158 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 GND VCC I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 GND I/O143 I/O142 I/O141 I/O140 VCC GND GND VCC I/O139 I/O138 I/O137 I/O136 GND I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 I/O129 I/O128 VCC GND I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0
TDO I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 VCC GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I3/CLK3 GND VCC I2/CLK2 I/O99 I/O98 I/O97 I/O96 GND I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 TMS
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5
4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2
2B8 2B11 2B12 2B13
3B13 3B12 3B11 3B8
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13
2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8
2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15
M5-384 M5LV-384 M5-320 M5LV-320
1B8 1B11 1B12 1B13
2B13 2B12 2B11 2B8
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0
Pin Designations
CLK GND I I/O NC
= = = = =
Clock Ground Input Input/Output No Connect
VCC TDI TCK TMS TDO
= = = = =
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
7
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
2A7 2A4 2A3 2A2
2B2 2B3 2B4 2B7
3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13
M5-512 M5LV-512
GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 VCC GND GND VCC I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
M5M5LV-
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0
D
15
Macrocell
PAL Block
Segment (
36
MACH 5 Family
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0
1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15
0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8
1A15 1A14 1A13 1A12 1A11 1A10 1A9 1A8
0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13
M5-320* M5LV-320* 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13
M5-320* M5LV-320*
Top View
*Package obsolete, contact factory.
Pin Designations
M5-384* M5LV-384* 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 0D7 0D6 0D5 0D4 0D3 0D2 0D1 0D0 1D8 1D9 1D10 1D11 1D12 1D13 1D14 1D15 0D15 0D14 0D13 0D12 0D11 0D10 0D9 0D8 1A13 1A12 1A11 1A8 1A7 1A4 1A3 1A2 0A2 0A3 0A4 0A7 0A8 0A11 0A12 0A13 M5-512* M5LV-512* TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 VCC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I0/CLK0 VCC GND I1/CLK1 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 GND I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
240-PIN PQFP CONNECTION DIAGRAM
CLK GND I I/O NC
7A13 7A12 7A11 7A8 7A7 7A4 7A3 7A2 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 0B2 0B3 0B4 0B7 0B8 0B11 0B12 0B13 7B0 7B1 7B2 7B3 7B4 7B5 7B6 7B7 7B8 7B9 7B10 7B11 7B12 7B13 5A15 5A14 5A13 5A12 5A11 5A10 5A9 5A8 5A7 5A6 5A5 5A4 5A3 5A2 4A15 4A14 4A13 4A12 4A11 4A10 4A9 4A8 4A7 4A6 4A5 4A4 4A3 4A2
M5-384* M5LV-384*
M5-512* M5LV-512*
= = = = =
Clock Ground Input Input/Output No Connect
1A7 1A6 1A5 1A4 1A3 1A2 1A1 1A0
1B2 1B3 1B4 1B7 1B8 1B11 1B12 1B13
2A13 2A12 2A11 2A8 2A7 2A4 2A3 2A2
VCC TDI TCK TMS TDO
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
2A15 2A14 2A13 2A12 2A11 2A10 2A9 2A8
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
= = = = =
1B8 1B9 1B10 1B11 1B12 1B13
2A7 2A6 2A5 2A4 2A3 2A2
2B8 2B9 2B10 2B11 2B12 2B13
240-Pin PQFP
Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
MACH 5 Family
2B13 2B12 2B11 2B10 2B9 2B8
2B2 2B3 2B4 2B5 2B6 2B7
3B13 3B12 3B11 3B10 3B9 3B8
6B13 6B12 6B11 6B10 9B9 6B8
5B2 5B3 5B4 5B5 5B6 5B7
4B2 4B3 4B4 4B5 4B6 4B7
7
2B7 2B6 2B5 2B4 2B3 2B2 2B1 2B0
2B8 2B9 2B10 2B11 2B12 2B13 2B14 2B15
3B7 3B6 3B5 3B4 3B3 3B2 3B1 3B0
6B7 6B6 6B5 6B4 6B3 6B2 6B1 6B0
5B8 5B9 5B10 5B11 5B12 5B13 5B14 5B15
4B8 4B9 4B10 4B11 4B12 4B13 4B14 4B15
D
15
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
3A2 3A3 3A4 3A7 3A8 3A11 3A12 3A13
GND VCC I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 GND I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 VCC GND GND GND GND VCC I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 GND I/O76 I/O77 I/O78 I/O79 I/O80 I/O81 I/O82 I/O83 VCC GND I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 VCC GND
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 TDO I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 VCC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 GND I/O123 I/O122 I/O121 I/O120 I/O119 I/O118 I/O117 I/O116 I3/CLK3 GND VCC I2/CLK2 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND VCC I/O99 I/O98 I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 TMS
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 155 184 183 182 181
GND VCC I/O183 I/O182 I/O181 I/O180 I/O179 I/O178 I/O177 I/O176 GND VCC I/O175 I/O174 I/O173 I/O172 I/O171 I/O170 I/O169 I/O168 GND I/O167 I/O166 I/O165 I/O164 I/O163 I/O162 VCC GND GND GND GND VCC I/O161 I/O160 I/O159 I/O158 I/O157 I/O156 GND I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 VCC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 VCC GND
6A2 6A3 6A4 6A7 6A8 6A11 6A12 6A13
4B13 4B12 4B11 4B8 4B7 4B4 4B3 4B2
3B13 3B12 3B11 3B8 3B7 3B4 3B3 3B2
Macrocell
Segment (
PAL Block
M5 M5LV
M5 M5LV
38
14
GND GND GND I/O108 I/O116 GND I/O128 I/O134 GND GND GND
20 A B
19
18
17
16
15
13
12
11
10
9
8
7
6
5
4
3
2
1
A
GND I/O11 GND I/O44 I/O58 GND I/O70 I/O76 GND
B
GND I/O12 I/O28 I/O45 I/O59 I/O64 I/O71 I/O77 I/O84 I/O90 I/O96 I/O102 I/O109 I/O117 I/O122 I/O129 I/O135 I/O148 I/O164 GND
C
VCC I/O79 I/O86 I/O92 I/O98 I/O104 I/O111 VCC I/O124 VCC
I/O0
I/O13
VCC
I/O46 I/O60 I/O65 I/O72 I/O78 I/O85 I/O91 I/O97 I/O103 I/O110 I/O118 I/O123 I/O130 I/O136 VCC I/O165 I/O181 C VCC I/O149 I/O166 I/O182 D TDO I/O150 I/O167 I/O183 E
Bottom View (I/O Pin-outs)
D
I/O1
I/O14 I/O29
VCC
VCC
I/O66
E
I/O2
I/O15 I/O30
TDI
*Package obsolete, contact factory.
CLK GND I I/O NC VCC TDI TCK TMS TDO
F
GND I/O16 I/O31 I/O47
I/O137 I/O151 I/O168 GND
F
VCC I/O152 I/O169 I/O184 G I/O138 I/O153 I/O170 GND I/O139 I/O154 I/O171 I/O185 I/O140 I/O155 I/O141 I/O156
I3/CLK3 I2/CLK2
G
I/O3
I/O17 I/O32
VCC
= = = = = = = = = =
H
GND I/O18 I/O33 I/O48
H J
I/O186 K GND
Pin Designations
J
I/O4
I/O19 I/O34 I/O49
K
GND
IO/CLK0
I/O35 I/O50
Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
256-Ball BGA
L
I/O5
I1/CLK1
I/O36 I/O51
L
I/O142 I/O157 I/O172 I/O187 M I/O143 I/O158 I/O173 GND
256-BALL BGA CONNECTION DIAGRAM -- M5-320, M5LV-320*, M5-384*, M5LV-384*, M5-512*, M5LV-512*
MACH 5 Family
VCC GND GND
M
I/O6
I/O20 I/O37 I/O52
N
GND I/O21 I/O38 I/O53
N
VCC I/O159 I/O174 I/O188 P I/O144 I/O160 I/O175 GND
P
I/O7
I/O22 I/O39
VCC
R
GND I/O23 I/O40 I/O54
R
TMS I/O161 I/O176 I/O189 T
T
I/O8
I/O24 I/O41
TCK I/O80 I/O87 I/O93 I/O99 I/O105 I/O112 VCC I/O125 VCC
U
I/O9
I/O25 I/O42
VCC
VCC
I/O67
VCC I/O162 I/O177 I/O190 U
V
I/O10 I/O26
VCC
I/O55 I/O61 I/O68 I/O73 I/O81 I/O88 I/O94 I/O100 I/O106 I/O113 I/O119 I/O126 I/O131 I/O145 VCC I/O178 I/O191 V
W
GND I/O27 I/O43 I/O56 I/O62 I/O69 I/O74 I/O82 I/O89 I/O95 I/O101 I/O107 I/O114 I/O120 I/O127 I/O132 I/O146 I/O163 I/O179 GND GND I/O115 I/O121 GND I/O133 I/O147 GND I/O180 GND
W Y 13 12 11 10 9 8 7 6 5 4 3 2 1
Y 14
GND
GND
GND I/O57 I/O63 GND I/O75 I/O83 GND
20
19
18
17
16
15
20
4A8 4A6 4A9 4A12 TDO 4A7 4A2 4B2 4B7 4B12 VCC 3B7 VCC VCC 3A2 3A4 3A7 VCC 4A5 4A1 4B1 4B5 4B9 4B13 3B12 3B4 3B3 VCC 4A3 4A0 4B0 4B3 4B6 4B10 4B11 4B15 3B11 3B8 3B2 3A3 3A8 4A4 GND GND GND GND 4B4 4B8 GND 4B14 3B13 GND GND GND GND 3A11 3D15 3A13 3D12 3A12 3D13 GND 3D14 3D11 3D10 3D6 3D1 2D1 2D6 2D11 VCC 3D5 3D0 2D0 2D5 2D9 2D14 3D9 3D8 3D4
I3/CLK3 I2/CLK2
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 A B C D E F
3D7 GND 3D3 3D2 GND
A
GND
0B2
GND 0B13 4A14 GND
B
GND
0A3
0B8
0B11 4A15 4A11 4A10
C
VCC
0D15
0A8
VCC
0B3
0B4
0B12 4A13
D
0D13 0A11
0A2
VCC
VCC
0B7
Bottom View (Macrocell Association)
*Package obsolete, contact factory.
E 4
0D10 0A13
0A4
TDI
CLK GND I I/O NC VCC TDI TCK TMS TDO
F D
GND 0D12 0A12
0A7
G
0D7
0D8
0D14
VCC
G H J K L
2D3 2D4 2D8 2D2 GND 2D7 2A11 2A14 2D12 GND TMS 2A10 2A15 2D10
= = = = = = = = = =
H 15
GND
0D4
0D9
0D11
Pin Designations
J
0D2
0D3
0D5
0D6
K
GND
IO/CLK0
0D0
0D1
256-Ball BGA
256-BALL BGA CONNECTION DIAGRAM -- M5-320, M5LV-320*
MACH 5 Family Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Segment (0-4) Macrocell (0-15) PAL Block (A-D)
VCC 1B2 1B5 1B7 1B6 1B9 1B3 1B8 1B13 2B13 2B8 1B10 1B14 2B14 2B10 1B12 1B15 2B15 2B12 1B11 GND GND GND 2B3 2B6 2B9 GND 2B11 VCC 2B2 2B5 2B7
L
1D2
I1/CLK1
1D0
1D1
M
1D3
1D4
1D5
1D6
M N P R T
2A4 2A1 2B4 GND VCC 2A5 2B0 2B1 VCC 2A6 2A2 2A0 2A8 VCC 2A3 GND 2A13 2D13 2A12 2D15 2A9 2A7 GND GND
N
GND
1D8
1D10 1D11
P
1D7
1D9
1D14
VCC
R
GND 1D13 1A14 1A11
T
1D12 1A15 1A10
TCK
U
1D15 1A12
1A8
VCC
VCC
1A4
U V W Y
V
1A13
1A9
VCC
1A6
1A5
1A1
W
GND
1A7
1A3
1A2
1B0
1B4
Y
GND
GND
GND
1A0
1B1
GND
40
15
5A8 5A6 5A9 5A12 TDO 5A7 5A2 5B2 5B7 5B12 VCC 4B7 VCC VCC 5A5 5A1 5B1 5B5 5B9 5B13 4B12 4B4 4B3 VCC 4A2 4A4 4A7 VCC 5A3 5A0 5B0 5B3 5B6 5B10 5B11 5B15 4B11 4B8 4B2 4A3 4A8 5A4 GND GND GND GND 5B4 5B8 GND 5B14 4B13 GND GND
20
19
18
17
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND GND 4A11 4D15
A
GND
0B2
GND 0B13 5A14 GND
A B C D
B
0B12 5A13 0B7 VCC
GND
0A3
0B8
0B11 5A15 5A11 5A10
C
0D15
0A8
VCC
0B3
0B4
D
0D13 0A11
0A2
VCC
VCC
E 5
0D10 0A13
0A4
TDI
4A13 4D12 4A12 4D13 GND 4D14 4D11 4D10 4D6 4D1 3D1 3D6 3D11 VCC 3A7 TMS 4D5 4D0 3D0 3D5 3D9 3D14 4D9 4D8 4D4
I3/CLK3 I2/CLK2
E F
4D7 GND 4D3 4D2 GND 3D3 3D4 3D8 3D2 GND 3D7 3A12 3D12 GND 3A4 3A13 3D10
CLK GND I I/O NC VCC TDI TCK TMS TDO
Bottom View (Macrocell Association)
*Package obsolete, contact factory.
F D
GND 0D12 0A12
0A7
G
0D7
0D8
0D14
VCC
G H J K L M N P R T
= = = = = = = = = =
H 15
GND
0D4
0D9
0D11
Pin Designations
J
0D2
0D3
0D5
0D6
K
GND
IO/CLK0
0D0
0D1
256-Ball BGA
Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
L
1D2
I1/CLK1
1D0
1D1
256-BALL BGA CONNECTION DIAGRAM -- M5-384*, M5LV-384*
MACH 5 Family Segment (0-5) Macrocell (0-15) PAL Block (A-D)
1B7 1B12 2A13 2A9 2A6 2A4 VCC 2A12 2A7 2A5 2A3 GND 2A2 2A1 2A0 GND 2B2 2B1 2B0 GND 2B7 2B5 2B3 GND 2B12 2B9 2B6 2B4 VCC 2A8 2B8
M
1D3
1D4
1D5
1D6
N
GND
1D8
1D10 1D11
P
1D7
1D9
1D14
VCC
R
GND 1D13 1A12
1A7
T
1D12 1A13
1A4
TCK 3B7 2B13 3B12 VCC 3B4
U
1D15
1A8
1A2
VCC
VCC
VCC 3B3 2B10 2B11 2B15 3B11
3A2 VCC 3B8 GND 2B14 3B13 GND
3A11 3D13 3A8 3A3 3B2 3D15 GND GND
U V W Y
V
1A11
1A3
VCC
1B3
1B4
W
GND
1B2
1B8
1B11 2A15 2A11 2A10
Y 15
GND
GND
GND 1B13 2A14 GND
20
19
18
17
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
GND 7B4 7A3 7A8 TDO VCC 7B3 7B8 7B13 6B13 6B8 6B3 VCC 6A8 VCC VCC 7B2 7B6 7B10 7B14 6B14 6B10 6B6 6B2 6A3 6A11 6A12 VCC 5A2 5A4 5A7 VCC 7B5 7B9 7B12 7B15 6B15 6B12 6B9 6B5 6B4 6B0 6A4 6A7 7B7 7B11 GND GND GND GND 6B11 6B7 GND 6B1 6A2 GND GND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
A
GND 7A13 GND
7A2
7B1
A B
B
GND
0A3
7A7
7A4
7B0
6A13 GND 5A3 5A8 5A11 5D15 5A13 5D12
C
0D15
0A8
VCC
7A12 7A11
C D E
D
0D13 0A11
0A2
VCC
VCC
E 5
0D10 0A13
0A4
TDI
Bottom View (Macrocell Association)
*Package obsolete, contact factory.
CLK GND I I/O NC VCC TDI TCK TMS TDO
F D
GND 0D12 0A12
0A7
5A12 5D13 GND 5D14 5D11 5D10 5D6 5D1 4D1 4D6 4D11 VCC 4A7 TMS 5D5 5D0 4D0 4D5 4D9 4D14 5D9 5D8 5D4
I3/CLK3 I2/CLK2
F
5D7 GND 5D3 5D2 GND 4D3 4D4 4D8 4D2 GND 4D7 4A12 4D12 GND 4A4 4A13 4D10
G
0D7
0D8
0D14
VCC
G H J K L M N P R T
= = = = = = = = = =
H 15
GND
0D4
0D9
0D11
Pin Designations
J
0D2
0D3
0D5
0D6
K
GND
IO/CLK0
0D0
0D1
256-Ball BGA
Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
L
1D2
I1/CLK1
1D0
1D1
256-BALL BGA CONNECTION DIAGRAM -- M5-512*, M5LV-512*
MACH 5 Family Segment (0-5) Macrocell (0-15) PAL Block (A-D)
2A8 2A3 2B4 GND 2B5 2B7 2B2 2B6 2B9 VCC 2B3 2B8 2B13 3B13 3B8 2B10 2B14 3B14 3B10 2B12 2B15 3B15 3B12 2B11 GND GND GND 3B3 3B6 3B9 GND 3B11 VCC 3B2 3B5 3B7
M
1D3
1D4
1D5
1D6
N
GND
1D8
1D10 1D11
P
1D7
1D9
1D14
VCC
R
GND 1D13 1A12
1A7
T
1D12 1A13
1A4
TCK 3A8 3A3 3B4 GND VCC
U
1D15
1A8
1A2
VCC
VCC
VCC 3A11 3A12 3B0 3B1 3A4 3A2
4A2 VCC 3A7
4A11 4D13 4A8 4A3 4D15 GND GND 3A13 GND
U V W Y
V
1A11
1A3
VCC
2A12 2A11
W
GND 2A13
2A7
2A4
2B0
Y 15
GND
GND
GND
2A2
2B1
20
19
18
17
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
42
18
GND I/O101 I/O95 I/O102 I/O107 I/O115 I/O122 I/O129 I/O135 I/O143 I/O150 I/O157 I/O163 I/O169 I/O176 I/O183 I/O188 GND I/O96 I/O103 I/O108 I/O116 I/O123 I/O130 I/O136 I/O144 I/O151 I/O158 I/O164 I/O170 I/O177 I/O184 VCC I/O104 I/O109 I/O117 VCC I/O131 I/O137 I/O145 VCC I/O159 I/O165 I/O171 I/O178 VCC NC NC NC NC NC NC NC I/O114 GND I/O128 I/O134 I/O142 GND I/O156 I/O162 GND NC GND NC GND NC NC
26 A B C D
NC
25
24
23
22
21
20
19
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
NC
GND
NC
I/O51
GND
I/O73
I/O80
I/O87
B
NC
GND
NC
I/O52
I/O68
I/O74
I/O81
I/O88
C
GND
I/O11
TDI
I/O53
I/O69
I/O75
I/O82
I/O89
D
I/O0
I/O12
I/O32
VCC
I/O70
I/O76
I/O83
I/O90
TDO I/O205 I/O224 GND I/O189 I/O206 I/O225
E
NC
I/O13
I/O33
I/O54
E F G
F
GND
I/O14
I/O34
I/O55
I/O190 I/O207 I/O226 I/O245 I/O191 I/O208 I/O227 GND VCC I/O209 I/O228 I/O246 I/O192 I/O210 I/O229 I/O247 VCC I/O211 I/O230 GND I/O193 I/O212 I/O231 I/O248 I/O194 I/O213 I/O232 I/O249 I/O195 I/O214 I/O233 I3/CLK3 VCC
I2CLK2 I/O234
Bottom View (I/O Pin-outs)
G
I/O1
I/O15
I/O35
VCC
H
I/O2
I/O16
I/O36
I/O56
H J K L M N
GND I/O196 I/O215 I/O235 I/O250 I/O197 I/O216 I/O236 I/O251 I/O198 I/O217 I/O237 I/O252 VCC I/O218 I/O238 GND I/O199 I/O219 I/O239 I/O253 VCC I/O220 I/O240 I/O254 I/O200 I/O221 I/O241 GND I/O201 I/O222 I/O242 NC
J
GND
I/O17
I/O37
VCC
K
I/O3
I/O18
I/O38
I/O57
CLK GND I I/O NC VCC TDI TCK TMS TDO
L
I/O4
I/O19
I/O39
I/O58
= = = = = = = = = =
M
I/O5
I/O20
I/O40
I/O59
Pin Designations
N
GND
I/O21 I0/CLK0
VCC
352-Ball BGA
P
I1/CLK1 I/O22
I/O41
I/O60
P R T U V W Y AA AB
352-BALL BGA CONNECTION DIAGRAM -- M5-512, M5LV-512
MACH 5 Family Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
I/O97 VCC I/O110 I/O118 I/O124 VCC I/O138 I/O146 I/O152 VCC
R
I/O6
I/O23
I/O42
I/O61
T
I/O7
I/O24
I/O43
I/O62
U
GND
I/O25
I/O44
VCC
V
I/O8
I/O26
I/O45
I/O63
W
I/O9
I/O27
I/O46
VCC
Y
GND
I/O28
I/O47
I/O64
20446G-030
A
I/O10
I/O29
I/O48
I/O65
B
NC
I/O30
I/O49
I/O66
C
GND
I/O31
I/O50
TCK
VCC
I/O77
I/O84
I/O91
I/O166 I/O172 I/O179 I/O185
VCC
I/O223 I/O243 I/O255
AC AD
D
NC
NC
NC
NC
I/O71
I/O78
I/O85
I/O92
I/O98 I/O105 I/O111 I/O119 I/O125 I/O132 I/O139 I/O147 I/O153 I/O160 I/O167 I/O173 I/O180 I/O186 I/O202 TMS I/O244 GND
26
GND 7B3 7B2 VCC 5A0 5A3 5A6 VCC 5A7 5A8 5A10 5A11 VCC 5D12 5D7 5D2 VCC 4D3 4D8 4D12 VCC 4A11 VCC 4A4 4A0 2A3 2A2 VCC 2B0 2B3 2B4 2B7 2B8 2B11 2B12 VCC 2B15 3B11 3B12 3B7 3B8 3B3 3B4 VCC 3B1 3A2 3A1 3A6 3A4 3A10 3A8 3A14 3A11 VCC 3A15 5A13 5D14 5D9 5D5 5D1
I2/CLK2
25
7B7 7B6 7B5 7B4 5A4 7B8 7B11 VCC 6B11 6B7 6B3 VCC 6A3 6A7 6A11 6A15 VCC TDO 5A1 5A2 5A5 5A9 5A14 5A15 5D13 5D10 5D8 5D4 5D0 4D0 4D4 4D7 4D11 4D14 4A14 4A10 4A7 4A5 4A2 TMS 4D2 4D6 4D10 4D13 4A15 4A12 4A9 4A8 4A3 4A1 7B9 7B12 6B15 6B12 6B8 6B4 6B0 6A2 6A5 6A8 6A10 6A13 NC NC NC NC GND NC 5A12 GND 5D15 5D11 GND 5D6 5D3
I3/CLK3
24
NC 7B10 7B13 7B15 6B13 6B9 6B5 6B2 6A0 6A4 6A6 6A9 6A12 6A14 GND NC NC 7B14 GND 6B14 6B10 6B6 GND 6B1 6A1 GND NC GND NC GND NC NC
23 A B C D E F G H J K L M N
GND 4D1 4D5 4D9 GND 4D15 4A13 GND NC 4A6 GND
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
NC
GND
NC
7A10
GND
7A5
7A0
7B1
B
NC
GND
NC
7A13
7A9
7A6
7A2
7B0
C
GND
0A1
TDI
7A14
7A11
7A7
7A3
7A1
D
0A6
0A3
0A2
VCC
7A15
7A12
7A8
7A4
E
NC
0A8
0A5
0A0
F
GND
0A9
0A7
0A4
Bottom View (I/O Pin-outs)
G
0A13
0A12
0A10
VCC
H
0D15
0A15
0A14
0A11
CLK GND I I/O NC VCC TDI TCK TMS TDO
J 7 D
GND
0D13
0D14
VCC
K
0D9
0D10
0D11
0D12
= = = = = = = = = =
L 15
0D5
0D6
0D7
0D8
Pin Designations
M
0D1
0D2
0D4
0D3
N
GND
0D0
I0/CLK0
VCC
352-Ball BGA
Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out
P
I1/CLK1
1D0
1D1
1D2
P R T U V W Y AA AB AC AD
352-BALL BGA CONNECTION DIAGRAM -- M5-512, M5LV-512
MACH 5 Family Macrocell (0-15) PAL Block (A-D)
R
1D3
1D4
1D5
1D7
Segment (0-7)
T
1D6
1D8
1D9
1D12
U
GND
1D10
1D14
VCC
V
1D11
1D13
1A13
1A11
W
1D15
1A15
1A10
VCC
Y
GND
1A14
1A8
1A6
AA
1A12
1A9
1A7
1A3
20446G-031
AB
NC
1A5
1A4
1A0
AC
GND
1A2
1A1
TCK
VCC
2A15
2A11
2A7
D
NC
NC
NC
NC
2A13
2A10
2A8
2A5
5V M5 ORDERING INFORMATION1,2
Lattice standard products are available in several packages and operating ranges. The order number (Valid Combinati by a combination of the elements below. . M5512 /256 -7 A C
FAMILY TYPE M5= MACH 5 (5-V VCC) MACROCELL DENSITY 128 = 128 Macrocells 192 = 192 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 /74 /104 /120 /160 /192 /256
PROGRAMMING DESIG Blank = Initial Algorith /1 = First Revision
OPERATING CONDITIO C = Commercial (0C I = Industrial (-40C
= = = = = = =
68 I/Os in 100-pin PQFP or TQFP 74 I/Os in 100-pin TQFP 104 I/Os in 144-pin PQFP or TQFP 120 I/Os in 160-pin PQFP 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA 256 I/Os in 352-ball BGA
PACKAGE TYPE Y = Plastic Quad Flat V = Thin Quad Flat P A = Ball Grid Array ( H = Plastic Quad Flat with exposed he SPEED -5 = 5.5 ns tPD -6 = 6.5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
.
Note: 1. See below for valid device/package combinations. 2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs. Valid Combinations M5-128/68 M5-128/104 M5-128/120 M5-192/68 M5-192/104 M5-192/120 M5-256/68 M5-256/104 M5-256/120 M5-256/160 *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5-512/256-7AC-10AI. Commercial: -5, -7, -10, -12, -15 Industrial: -7, -10, -12, -15, -20 YC, VC, YI, VI YC, YI YC, YI YC*, VC, YI*, VI YC*, YI* YC, YI YC*, VC, YI*, VI YC*, YI* YC, YI YC, YI M5-320/120 M5-320/160 M5-320/184 M5-320/192 M5-384/120 M5-384/160 M5-384/184 M5-384/192 M5-512/120 M5-512/160 M5-512/184 M5-512/192 M5-512/256
Valid Combinations
H
HC, Y
H Commercial: -6, -7, -10, -12, -15 Industrial: -7, -10, -12, -15, -20
A
H
HC, Y
H
A
H
HC, Y
H
A
A Valid Combinations
Valid Combinations list configurations pla supported in volume for this device. Consult the sales of fice to confir m availability of sp combinations and to check on newly released co
44
MACH 5 Family
3.3V M5LV ORDERING INFORMATION1
Lattice standard products are available in several packages and operating ranges. The order number (Valid Combinati by a combination of the elements below. M5LV512 /256 -7 A C
FAMILY TYPE M5LV- = MACH 5 Low Voltage (3.3-V VCC) MACROCELL DENSITY 128 = 128 Macrocells 256 = 256 Macrocells 320 = 320 Macrocells 384 = 384 Macrocells 512 = 512 Macrocells I/Os /68 /74 /104 /120 /160 /192 /256
OPERATING CONDITIO C = Commercial (0C I = Industrial (-40C
PACKAGE TYPE Y = Plastic Quad Flat V = Thin Quad Flat P A = Ball Grid Array ( H = Plastic Quad Flat with exposed hea
= = = = = = =
68 I/Os in 100-pin PQFP or TQFP 74 I/Os in 100-pin TQFP 104 I/Os in 144-pin PQFP or TQFP 120 I/Os in 160-pin PQFP 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA 256 I/Os in 352-ball BGA
SPEED -5 = 5.5 ns tPD -6 = 6.5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
Note: 1. See below for valid device/package combinations.
Valid Combinations M5LV-128/68 M5LV-128/74 M5LV-128/104 M5LV-128/120 M5LV-256/68 M5LV-256/74 M5LV-256/104 M5LV-256/120 M5LV-256/160 *Package obsolete, contact factory. ** Contact Factory for availability. Device Marking Actual device marking differs from the ordering part number (OPN). All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e., M5LV-512/256-7AC-10AI. Industrial: -7, -10, -12, -15 Commercial: -5, -7, -10, -12 YC*, VC, YI*, VI VC, VI YC*, VC, YI*, VI YC, YI YC, VC*, YI, VI* VC, VI YC*, VC, YI*, VI YC, YI YC, YI M5LV-320/120 M5LV-320/160 M5LV-320/184 M5LV-320/192 M5LV-384/120 M5LV-384/160 M5LV-384/184 M5LV-384/192 M5LV-512/120 M5LV-512/160 M5LV-512/184 M5LV-512/192 M5LV-512/256
Valid Combinations
HC, Y
HC, Y
H Commercial: -6, -7, -10, -12, -15 Industrial: -10, -12, -15, -20
A
HC, Y
HC, Y
H
A
HC, Y
HC, Y
H
A
Valid Combinations
Valid Combinations list configurations pla supported in volume for this device. Consult the sales of fice to confir m availability of sp combinations and to check on newly released co
MACH 5 Family
46
MACH 5 Family, 3.3-V Ind
MACH 5 Family, 3.3-V Ind

▲Up To Search▲

Price & Availability of M5-128120-5YI

	To Download M5-128120-5YI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .